Final version of RCL tester. - Help me choose components. Frequency dividers.
i want send impulse rcl circuit , measure self frequency, amplitude decay , time next pulse in such way gives rcl push without subtracting existent oscillations or effecting resonance frequency.
a self-tuning generator.
i decided circuit should this.
maybe there optimized ic solution, haven't found 1 yet.
how fast can asynchronous buffers go before missing step?
i thinking of using 2 programmable counters - 1 trip when "1" byte comes out of buffer , 1 long - term self-frequency measurement of rcl circuit.
for counter need along lines http://www.jameco.com/jameco/products/prodds/2178988.pdf(
)
for buffer ic, not sure for.
my "1" has shorter my microcontroller can create, since test high impedance rcl circuits -- rcl ring while. give arduino time calculate when next pulse should generated meets crest of self-oscillation wave.
this idea behind self-tuning circuit.
rcls have self-frequency @ 100khz 1mhz clock serves buffer , synchronous dividers have run @ least 100 times faster.
also have know exact # of clock cycles takes arduino perform amount of commands. possible?
a self-tuning generator.
i decided circuit should this.
maybe there optimized ic solution, haven't found 1 yet.
how fast can asynchronous buffers go before missing step?
i thinking of using 2 programmable counters - 1 trip when "1" byte comes out of buffer , 1 long - term self-frequency measurement of rcl circuit.
for counter need along lines http://www.jameco.com/jameco/products/prodds/2178988.pdf(
)for buffer ic, not sure for.
my "1" has shorter my microcontroller can create, since test high impedance rcl circuits -- rcl ring while. give arduino time calculate when next pulse should generated meets crest of self-oscillation wave.
this idea behind self-tuning circuit.
rcls have self-frequency @ 100khz 1mhz clock serves buffer , synchronous dividers have run @ least 100 times faster.
also have know exact # of clock cycles takes arduino perform amount of commands. possible?
are sure supposed pnp transistor ?
your drawing combination of block diagram , quasi-schematic lacks enough info used schematic. why have pnp transistor ?
you drawing shows 100mhz 1ghz clock. post says 100khz 1mhz. ?
this design. easy add instruction cycle times answer question. can using attached document.
your drawing combination of block diagram , quasi-schematic lacks enough info used schematic. why have pnp transistor ?
you drawing shows 100mhz 1ghz clock. post says 100khz 1mhz. ?
quote
this idea behind self-tuning circuit.
rcls have self-frequency @ 100khz 1mhz clock serves buffer , synchronous dividers have run @ least 100 times faster.
also have know exact # of clock cycles takes arduino perform amount of commands. possible?
this design. easy add instruction cycle times answer question. can using attached document.
Arduino Forum > Using Arduino > Project Guidance > Final version of RCL tester. - Help me choose components. Frequency dividers.
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